PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 326

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

RFS…
ISF…
RMB…
RSC…
CRC6…
PDEN…
RPF…
Data Sheet
The complete message length can be determined reading the RBCH,
RBCL registers, the number of bytes currently stored in RFIFO is
given by RBC4...0. Additional information is available in the RSIS
register.
Receive Frame Start
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an RFS
interrupt, the contents of RSIS.3...1 is valid and can be read by the
CPU.
Incorrect Sync Format
The FALC
in BOM mode. Only valid if BOM receiver has been activated.
Receive Multiframe Begin
This bit is set with the beginning of a received multiframe of the
receive line timing.
Received Signaling Information Changed
This interrupt bit is set during each multiframe in which signaling
information on at least one channel changes its value from the
previous multiframe. This interrupt only occurs in the synchronous
state. The registers RS1...6/RS1...12 should be read within the next
3 ms otherwise the contents may be lost.
Receive CRC6 Error
0…
1…
Pulse Density Violation
The pulse density violation of the received data stream defined by
ANSI T1. 403 is violated. More than 15 consecutive zeros or less than
N ones in each and every time window of 8 (N+1) data bits (N=23)
are detected. If IPC.SCI is set high this interrupt status bit is activated
with every change of state of FRS1.PDEN.
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not
yet received completely.
No CRC6 error occurs.
The CRC6 check of a received multiframe failed.
®
-LH could not detect eight consecutive one’s within 32 bits
326
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07