PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 159

IC INTERFACE LINE 80-MQFP

PEB2255H-V13

Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2255H-V13

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
Table 39
Register
LOOP
XSW
XSP
TSWM
XC0
XC1
RC0
RC1
IDLE
ICB 1 … 4
LIM0
LIM1
PCD
PCR
XPM2...0
IMR0...4
RTR1...4
TTR1...4
MODE
PRE
RAH1/2
RAL1/2
E1 Initialization
For a correct start up of the Primary Access Interface a set of parameters specific to the
system and hardware environment must be programmed after reset goes inactive. Both
the basic and the operational parameters must be programmed before the activation
procedure of the PCM line starts. Such procedures are specified in ITU-T and ETSI
recommendations (e.g. fault conditions and consequent actions). Setting optional
parameters primarily makes sense when basic operation via the PCM line is guaranteed.
Table 40
control bits which are to be programmed in one of the above steps. The sequence is
recommended but not mandatory. Accordingly, parameters for the basic and operational
Data Sheet
gives an overview of the most important parameters in terms of signals and
Reset Value Meaning
00
40
00
00
00
9C
00
9C
00
00
00
00
00
00
7B
FF
FF
00
00
00
00
FD
FF
Initial Values after Reset (E1) (cont’d)
H
H
H
H
H
H
H
H
H
H
H
H
H,
H,
H
H
H
H,
H,
H
H
H
H
,03
, FF
00
, FF
FF
FF
H,
H
H,
H,
H
00
,00
H
FF
H,
H
H,
Channel loop back and single frame mode are disabled.
All bits of the transmitted service word are cleared (bit 2
excluded). Spare bit values are cleared.
No transparent mode active.
The transmit clock offset is cleared.
The transmit time slot offset is cleared.
The receive clock slot offset is cleared; 1st channel phase
is active on PCM highway.
The receive time slot offset is cleared.
Idle channel code is cleared.
Normal operation (no ‘Idle Channel’ selected).
Slave Mode, Local Loop off, CLKX=2.048 MHz active high,
short haul mode, no LOS indication on RCLK
Analog interface selected, Remote Loop off
Pulse Count for LOS Detection cleared
Pulse Count for LOS Recovery cleared
Transmit Pulse Mask
All interrupts are disabled
No time slots selected
Signaling controller disabled
Preamble cleared
Compare register for receive address cleared
159
Operational Description E1
FALC-LH V1.3
PEB 2255
2000-07

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