PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 91

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Sa6 Bit Error Indication Counters
The Sa6 bit error indication counter CRC2L/H (16 bits) counts the received Sa6 bit
sequence 0001 or 0011 in every CRC submultiframe. In the primary rate access digital
section this counter option gives information about CRC errors reported from the TE via
Sa6 bit. Incrementing is only possible in the multiframe synchronous state.
The Sa6 bit error indication counter CRC3L/H (16 bits) counts the received Sa6 bit
sequence 0010 or 0011 in every CRC submultiframe. In the primary rate access digital
section this counter option gives information about CRC errors detected at T-reference
point and reporting them via the Sa6 bit. Incrementing is only possible in the multiframe
synchronous state.
4.4.3.8
Due to signaling requirements, the E bits of frame 13 and frame 15 of the CRC
multiframe can be used to indicate received errored submultiframes:
Submultiframe I status E- Bit located in frame 13
Submultiframe II status E- Bit located in frame 15
no CRC error:
CRC error:
Standard Procedure
After reading the Submultiframe Error Indication RSP.SI1 and RSP.SI2, the
microprocessor has to update contents of register XSP (XS13, XS15). Access to these
registers has to be synchronized with Transmit or Receive Multiframe Begin Interrupts
(ISR0.RMB or ISR1.XMB).
Automatic Mode
In the multiframe synchronous state the E-bits are processed according to ITU-T G.704
independently of bit XSP.EBP (E-bit polarity selection).
By setting bit XSP.AXS status information of received submultiframes is automatically
inserted in the E-bit position of the outgoing CRC multiframe without any further
interventions of the microprocessor.
In the doubleframe and multiframe asynchronous state the E-bits are set or cleared,
depending on the setting of bit XSP.EBP.
Submultiframe Error Indication Counter
The EBC (E-Bit) Counter EBCL and EBCH (16 bits) counts zeros in E-bit position of
frame 13 and 15 of every received CRC Multiframe. This counter option gives
information about the outgoing transmit PCM line if the E bits are used by the remote end
Data Sheet
E-Bit Access (E1)
:
:
E = 1
E = 0
91
Functional Description E1
FALC-LH V1.3
PEB 2255
2000-07