CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 136

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

5.0 Reassembly Coprocessor
5.6 Status Queue Operation
5-28
of Status Queue Entries
5.6.1.4 Host Detection
5.6.1.3 Errors
The RSM coprocessor also writes a status entry for several error conditions:
reassembled on channels having free buffer queues in the empty state, a BOM cell
causes a status queue entry to be written. If a BOM cell is received and no early
packet discards have occurred on channels mapped to the empty free buffer
queue, status queue entry is written with the BOM and UNDF bits set to a logic
high. In addition, the RSM_HF_EMPT bit in the HOST_ISTAT1 register is set to
a logic high. This status does not point to a linked list of buffer descriptors. It is
written a maximum of once per free buffer queue empty condition.
The host can use either a polling operation or an interrupt routine to detect new
status queue entries.
current READ position until it returns a logic high. The host then processes the
status entry, writes the VLD bit to a logic low and increments its current READ
pointer. Periodically, the host writes the current READ index value into the
READ_UD field of the status queue base table entry.
reassembly coprocessor writes a status queue entry into host memory, the
HOST_ISTAT0 (RSM_HS_WRITE) bit is set to a logic high to prompt an
interrupt. Upon receiving an interrupt, the host reads HOST_ST_WR
(RSM_HS_WRITE[15:0]) to determine which host memory status queue(s)
caused the interrupt. See
NOTE:
HOST_ISTAT1 upon receiving an interrupt, and periodically read
HOST_ISTAT0 to ensure that no error conditions have occurred. Once the
interrupt manager has determined which status queue(s) caused the interrupt, the
host starts reading the appropriate status queues at their current read location. The
host processes status entries until reading an entry with the VLD bit set to logic
low. Again, the host periodically writes the current READ index value into the
READ_UD field of the status queue base table entry.
• Reassembly time-out
• Early packet discard
• Per-channel firewall
• CPCS abort
To ensure that an error indication occurs even if no CPCS-PDUs are being
To poll each status queue, the host continuously reads the VLD bit at the
The host can also use an interrupt routine to process status queues. When the
A typical operation for the interrupt manager would be to only read
Only status queues 0 through 15 are reported in this register.
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Section 3.3.2.4
™
for alternative methods.
28237-DSH-001-C
CN8237