CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 21

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
Figure 8-12.
Figure 8-13.
Figure 8-14.
Figure 8-15.
Figure 8-16.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10.
Figure 16-11.
Figure 16-12.
Figure 16-13.
Figure 16-14.
Figure 16-15.
Figure 16-16.
Figure 16-17.
Figure 16-18.
Figure A-1.
Figure A-2.
Little Endian Host Slave Interface Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
Big Endian 64-bit Master Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Big Endian 32-bit Master Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Big Endian SAR as Master Control Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Big Endian Host Slave Interface Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
ZBT or Syncburst Synchronous SRAM Bank Utilizing By_16 Devices. . . . . . . . . . . . . . . . 10-4
SAR (CN8237) and OC-3 PHY (RS825x) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
CN8237/PHY Functional Timing with Inserted Wait States (Normal Mode). . . . . . . . . . . . 11-3
CN8237/RS825x Read/Write Functional Timing (Normal Mode) . . . . . . . . . . . . . . . . . . . 11-4
Typical PHY Connection to RS825x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Typical PHY Connection to RS8228. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
EEPROM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
UTOPIA Level 2 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Receive Timing in UTOPIA Level 1 Mode with Cell Handshake . . . . . . . . . . . . . . . . . . . . 13-10
Transmit Timing in UTOPIA Level 1 Mode with Cell Handshake . . . . . . . . . . . . . . . . . . . 13-11
Receive Timing in UTOPIA Level 1 Mode with Octet Handshake . . . . . . . . . . . . . . . . . . . 13-12
Transmit Timing in UTOPIA Level 1 Mode with Octet Handshake . . . . . . . . . . . . . . . . . . 13-12
Receive Timing in Slave UTOPIA Level 1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Transmit Timing in Slave UTOPIA Level 1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
Source Loopback Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
PCI Bus Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
PCI Bus Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
UTOPIA and Slave UTOPIA Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . 16-5
UTOPIA and Slave UTOPIA Output Timing Measurement Conditions . . . . . . . . . . . . . . . . 16-5
ZBT Flow Through SRAM Timing Diagram—One Cycle Memory . . . . . . . . . . . . . . . . . . . 16-6
ZBT Flow Through SRAM Memory Timing Diagram—Two Cycle Memory . . . . . . . . . . . . 16-7
Memory Interface to Syncburst Flow Through SRAM Timing—One Cycle Memory . . . . . 16-8
Memory Interface to Syncburst Flow Through SRAM Timing—Two Cycle Memory . . . . . 16-9
SAR’s Local Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Add a Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
Flight Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
Recommended PCB Trace Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Recommended PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
CN8237/PHY Functional Timing with Inserted Wait States (Normal Mode). . . . . . . . . . . 16-15
Interface Timing Diagram—Strobed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
RS8223 PHY Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
456-Pin Ball Grid Array Package (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
CN8237 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
Test Circuitry Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Mindspeed Technologies
™
List of Figures
xv