CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 257

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Figure 11-4. Typical PHY Connection to RS825x
28237-DSH-001-C
CN8237 (SAR)
11.3 Microprocessor Interface for Multiple
Physical Devices
Multi-PHY or extended addressing for a PHY is provided through a PHY page
mechanism. This allows address bits to be appended to PHY control access
without increasing the size of the PHY memory map as seen by the PCI. The
PHY BANK field in the CONFIG1 control register provides up to five bits of
page addressing for a total of 13 bits of PHY addressing. The contents of PHY
BANK are placed on PADDR[12:8] during PCS* access.
required. Likewise, PWAIT* is only required where the returned read data is
expected to be variable or slower than four PCLK clock cycles. In the event the
PHY device does not require externally controlled wait states, the PWAIT* signal
can be tied high. In a multi-device connection, this signal may be supported via a
pull-up in typical wired-OR fashion. None of the devices shown in this document
require externally provided PWAIT* control.
NOTE:
pullup resistors. This pull-up function is not provided at the PINT* input.
package I/O and some typical PHY devices. CN8237 signals ending in ’*’ are
active low.
NOTE:
PADDR[8:0]
PDATA[7:0]
The PDS* connection is only required where a data strobe handshake signal is
The PHY interrupt outputs shown here are open-drain outputs and require
Figure 11-4
PWAIT*
In some applications, due to the specific timing of the interface signals,
use of the PWAIT* signal can needlessly slow down the interface.
PHY parts in these diagrams use the ’~’ notation to denote the same.
PRST*
PWNR
PINT*
PCLK
PCS*
PDS*
PAS*
Mindspeed Technologies
and
Figure 11-5
VDD
VDD
VDD
11.3 Microprocessor Interface for Multiple Physical Devices
show the signal interface between the PHY block
Reset~
MCLK
Cs~
AS~
SSYNCMODE
W/R~
DATA[7:0]
ADDR[8:0]
Int~
™
RS825x (PHY)
11.0 PHY Interface
8237_130
11-5