CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 284

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

13.0 ATM UTOPIA Interface
13.6 UTOPIA Level 1 Mode Octet Handshake Timing
Figure 13-4. Receive Timing in UTOPIA Level 1 Mode with Octet Handshake
Figure 13-5. Transmit Timing in UTOPIA Level 1 Mode with Octet Handshake
13-12
NOTE(S):
(1)
(2)
TXD/TXPAR
(TXFLAG*)
(TXMARK)
RXD/RXPAR
NOTE(S):
(1)
TxEN* goes active if TxClav (TxFlag*) is inactive at previous rising clock edge and a complete cell in the transmit FIFO buffer.
TxEN* goes inactive one to four clock cycles after TxClav goes active.
(RXFLAG*)
TXCLAV
(RXMARK)
TXSOC
TXCLK
TXEN*
RXCLAV
RxEN* goes inactive only if there is no room for another octet in the receive FIFO buffer.
RXSOC
RXCLK
RXEN*
X
H1
(1)
H1
H2
TxEN* is asserted. TxEN* is only asserted when there is data in the CN8237
transmit FIFO buffer. Simultaneously, odd parity computed over the
TxDATA[15:0] lines is driven on to the TxPAR output. The TxSOC (TxMARK)
line is driven by the SAR to indicate start of cell. If the TxCLAV (TxFLAG*)
input is asserted by the framer device, the framer device is full and can accept
only one to four more octets. (See
output, which is a 50% duty cycle, two-thirds of RCLK0.
Transmit data is driven on TxDATA[15:0] on the rising edge of TxCLK when
In UTOPIA mode, the TxClk input can be connected to the CN8237 CLKD3
***
H3
(1)
Mindspeed Technologies
P44
X
P45
H4
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
P46
X
Figure
P47
H5
(2)
™
13-5.)
***
X
P48
X
H1
P48
28237-DSH-001-C
H2
H1
CN8237
H3
H2
8237_098
8237_099