CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 66

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (3 of 6)
2-32
FRCFG
TxDATA[15:0]
TxADDR[4:0]
TxPAR
TxSOC
TxCLAV
(TxFLAG*)
TxEN*
TxCLK
RxADDR[4:0]
RxDATA[15:0]
RxPAR
RxSOC
(RxMARK)
RxCLAV
(RxFLAG*)
RxEN*
Pin Label
ATM Physical Interface
Configuration
Transmit Data
Transmit Address
Transmit Data Parity
Transmit Cell Marker
Transmit Flag
Transmit Enable
Transmit clock
Receive Address
Receive Data
Receive Data Parity
Receive Cell Marker
Receive Flag
Receive Enable
Signal Name
Mindspeed Technologies
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
(1)
Configuration pin FRCFG determines what ATM physical
interface the CN8237 supports.
1 = UTOPIA interface master.
0 = Slave UTOPIA interface.
Carries outgoing data bytes to the PHY chip in all framer
modes (8 mA drive).
UTOPIA transmit address. 8 mA drive.
Outputs the odd parity computed over the 8 or 16 data
lines in all framer modes.
In both UTOPIA and slave UTOPIA modes, the TxSOC line
is asserted by the CN8237 when the starting byte of a
53-byte cell is being output.
In UTOPIA mode, TxCLAV (TxFLAG*) indicates that the
transmit buffer in the downstream link interface chip is full
and no more data can be accepted. In slave UTOPIA mode,
this pin indicates to the link interface chip that the CN8237
transmit buffer is empty.
Indicates that valid data has been placed on the
TxDATA[15:0], TxPAR, and TxSOC lines in the current
clock cycle when the CN8237 is in UTOPIA or slave
UTOPIA mode. This pin is an output in UTOPIA mode and
an input in slave UTOPIA mode.
UTOPIA transmit clock.
UTOPIA receive address.
Transfers incoming data bytes from the link interface or
framer chip to the CN8237 in all framer modes.
Should be driven with the odd parity computed over the 8
or 16 data lines by the link interface or framer chip in all
framer modes.
Indicates that the current byte being transferred on the
RxDATA[7:0] lines is the starting byte of a 53-byte cell.
In UTOPIA mode, RxCLAV (RxFLAG*) indicates that the
receive buffer in the downstream link interface chip is
empty, no more data can be transferred, and the
RxDATA[7:0], RxPAR, and RxSOC (RxMARK) lines are
invalid. In slave UTOPIA mode, this pin indicates to the
framer chip that the receive FIFO buffer in the CN8237 is
full.
In UTOPIA mode, RxEN* indicates that the CN8237 is
ready to receive data on the RxDATA[15:0], RxPAR, and
RxSOC (RxMARK) lines in the next clock cycle. This pin is
an output in UTOPIA mode and an input in slave UTOPIA
mode.
™
Definition
28237-DSH-001-C
CN8237