CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 296

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

14.0 CN8237 Registers
14.2 System Registers
0x28
14-6
23–21
20–19
17–16
Bit
31
30
29
28
27
26
25
24
18
—
Configuration Register 0 (CONFIG0)
Field
Size
1
1
1
1
1
1
1
1
3
2
1
2
Reserved
GLOBAL_RESET
PCI_MSTR_RESET
PCI_ERR_RESET
Reserved
INT_LBANK
MEMTYPE
MEMCTRL
BANKSIZE[2:0]
NUMBANKS[1:0]
PCI_READ_MULTI
PCI_ARB[1:0]
This register provides all of the control and configuration bits that are not
associated with the reassembly and segmentation coprocessors. The majority of
these configuration bits are set at initialization time and are not changed
dynamically. The assertion of the HRST* system reset pin clears all of the bits in
the CONFIG0 register except for MEMCTRL, which will be set high.
Name
Mindspeed Technologies
Always set to 0.
When set, this bit causes reset of the segmentation and reassembly
coprocessors as well as all latched status.
When set, this bit resets the PCI master logic. Once active, this bit must
stay active for 16 cycles of the HCLK input signal.
When set, resets all PCI error bits in the PCI configuration, including RMA,
RTA, DPR, INTF_DIS, INT_FAIL, and MERROR. This also re-enables PCI
master operation.
Always set to 0.
When set, allows only byte 0 and 1 writes to odd quad word addresses in
address space 0x1000 – 0x10ff and 0x1400 – 0x14ff. This allows endian
neutral access of the Status Queue Base Table READ_UD field by the host
processor.
Logic high selects non-zbt memory. Logic low selects zbt memory.
Selects 0 or 1 wait states SRC shared memory (1 or 2 cycle). Reset to a
logic high (1 wait state operation).
Selects size of memory banks for contiguous memory support.
Selects the number of RSM and SEG memory banks that are active.
When this bit is set, the SAR’s PCI Master implements the PCI Read
Multiple Command. Otherwise, the PCI Master implements the PCI Read
Command.
Selects PCI Master arbitration scheme.
111 – 8 MB
110 – 4 MB
101 – 2 MB
100 – 1 MB
011 – 512 KB
010 – 256 KB
001 – 128 KB
000 – Reserved
0 – 1 bank active
1 – 2 banks active
2 – 4 banks active
3 – not used
00 – read priority over write
01 – round robin
10 – write priority over read
11 – not used
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
Description
28237-DSH-001-C
CN8237