CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 64

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (1 of 6)
2-30
HAD[63:0]
HCBE[7:0]*
HPAR
HPAR64
HFRAME*
HIRDY*
HTRDY*
HSTOP*
HDEVSEL*
Pin Label
Multiplexed
Address/Data Bus
Command/Byte Enable
Address/Data
Command Parity
Address/Data
Command Parity
Upper DWORD
Transaction Initiator
Ready
Transaction Target
Ready
Transaction Termination
Bus Device
Acknowledge
Framing Signal
Signal Name
Mindspeed Technologies
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
(1)
Used by the PCI host or CN8237 to transfer addresses or
data over the PCI bus.
Outputs a command (during PCI address phases) or byte
enables (during data phases) for each bus transaction.
Supplies the even parity computed over the HAD[31:0]
and HCBE[3:0]* lines during valid data phases. It is
sampled (when the CN8237 is acting as a target) or driven
(when the CN8237 acts as an initiator) one clock edge
after the respective data phase.
Supplies the even parity computed over the HAD[63:32]
and HCBE[7:4]* lines during valid data phases. It is
sampled (when the CN8237 is acting as a target) or driven
(when the CN8237 acts as an initiator) one clock edge
after the respective data phase.
A high-to-low HFRAME* transition indicates that a new
transaction is beginning (with an address phase). A
low-to-high transition indicates that the next valid data
phase will end the current transaction.
Used by the transaction initiator or bus master (either the
CN8237 or the PCI host) to indicate ready for data
transfer. A valid data transfer occurs when both HIRDY*
and HTRDY* are active on the same clock edge.
Used by the transaction target or bus slave (either the
CN8237 or the PCI bus memory) to indicate that it is ready
for a data transfer. A valid data transfer occurs when both
HIRDY* and HTRDY* are active on the same clock edge.
Driven by the current target or slave (either the CN8237 or
the PCI bus memory) to abort, disconnect, or retry the
current transfer. The HSTOP* line is used by the PCI
master in conjunction with the HTRDY* and HDEVSEL*
lines to determine the type of transaction termination.
Driven by a target to indicate to the initiator that the
address placed on the HAD[31:0] lines (together with the
command on the HC/BE[3:0]* lines) has been decoded
and accepted as a valid reference to the target’s address
space. Once asserted, it is held by the CN8237 (when
acting as a slave) until HFRAME* is deasserted; otherwise,
it indicates (in conjunction with HSTOP* and HTRDY*) a
target abort.
™
Definition
28237-DSH-001-C
CN8237