CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 324

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

14.0 CN8237 Registers
14.7 PCI Bus Interface Registers
Table 14-4. PCI Configuration Field Descriptions (1 of 2)
14-34
DEVICE_ID
VENDOR_ID
STATUS
COMMAND
CLASS_CODE
REV_ID
HEADER_TYPE
LAT_TIMER
CACHE_LINE_SIZE
BASE_ADDRESS
_REGISTER_0
SUBSYSTEM_ID
(SID)
SUBSYSTEM
_VENDOR_ID (SVID)
CAPABILITY_PTR
MAX_LATENCY
MIN_GRANT
INTERRUPT_PIN
Field
16-bit device identifier. Serves to uniquely identify the SAR to the host operating system. Set to
0x8237.
16-bit vendor identifier code, allocated on a global basis by the PCI Special Interest Group. Set to
0x14F1.
PCI bus interface status register. The PCI host can monitor its operation using the STATUS field. This
field is further divided into subfields. These bits can be reset by writing a logic high to the appropriate
bit. See
PCI bus interface control/command register. The PCI host can configure the SAR bus interface logic
using the COMMAND field. This field is further divided into subfields. Active HRST* input causes all
bits to be a logic 0. See
The CLASS_CODE register is read-only and is used to identify the generic function of the device. See
PCI Bus Specification, Revision 2.1 for the specific allowed settings for this field. Set to 0x020300
(indicates a network controller, specifically an ATM controller).
Revision ID code for the CN8237 chip; 0=Rev A, 1=Rev B, 2=Rev C. Modify per bond-out option.
This field identifies the layout of the second part of the predefined header of the PCI Configuration
space (beginning at 0x10). See PCI Local Bus Specification, Revision 2.1 for the specific possible
settings for this field. Set to 0x00.
Latency timer. Value after HRST* active is 0x00. All bits are writable. The suggested value is 0x10 in
order to allow the complete transfer of a cell.
This read/write register specifies the system cacheline size in units of 32-bit words. Must be initialized
to 0x00 at initialization and reset.
Base address of PCI address space occupied by the CN8237 (as seen and assigned by the host
processor). Value after HRST* active is 0x00000000.
This register value is used to uniquely identify the add-in board or subsystem where the PCI device
resides. Thus, it provides a mechanism for add-in card vendors to distinguish their cards from one
another even though the cards can have the same PCI controller on them (and therefore the same
DEVICE_ID).
This register value is used to uniquely identify the vendor of an add-in board or subsystem where the
PCI device resides. Thus, it provides a mechanism for add-in card vendors to distinguish their cards
from one another even though the cards can have the same PCI controller on them (and therefore the
same VENDOR_ID).
This field provides an offset into the PCI Configuration space for the location of the first item in the
Capabilities Linked List. Set to 0x50.
This read-only register specifies how often the CN8237 device needs to gain access to the PCI bus,
assuming a clock rate of 33 MHz. Set to 0x05 (a period of time in units of 1/4 microseconds).
This read-only register specifies how long of a burst period the CN8237 device needs to gain access to
the PCI bus. Set to 0x02 (a period of time in units of 1/4 microseconds).
This read-only register tells which interrupt pin the device (or device function) uses. Set to 0x01
(corresponds to interrupt pin INTA*).
Table 14-6
Status register breakdown. The PCI Special Status register is detailed in
Table
Table 14-5
14-7.
Mindspeed Technologies
for a description of the bits in the register.
details the PCI Command register and
Table 14-8
Table 14-6
details the EPROM register.
for a description of the bits in the register.
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Description
™
Table 14-5
shows the PCI
28237-DSH-001-C
CN8237