CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 65

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (2 of 6)
28237-DSH-001-C
HIDSEL
HREQ*
HGNT*
HINTA*
HACK64*
HM66EN
HPERR*
HSERR*
HCLK
HRST*
PCILITE
HSWITCH*
HLED*
HENUM*
HREQ64*
Pin Label
Bus Device Slot Select
Interrupt Request
64-bit transfer request
acknowledged
PCI clock speed select
Bus Parity Error
System Error
Bus Clock
System Reset
Bus Signalling
Switch indicator
LED power
ENUM*
64-bit transfer request
Arbiter Bus Request
Bus Grant
Signal Name
Mindspeed Technologies
I/O
OD
OD
OD
OD
I/O
I/O
I/O
O
I
I
I
I
I
I
I
(1)
Signals the CN8237 that it is being selected for a
configuration space access.
Asserted by the CN8237 to request control of the PCI bus.
Asserted to indicate to the CN8237 that it has been
granted control of the PCI bus, and can begin driving the
address/data and control lines after the current transaction
has ended (indicated by HFRAME*, HIRDY*, and
HTRDY*; all deasserted simultaneously).
Signals an interrupt request to the PCI host, and is tied to
the INTA_ line on the PCI bus.
Driven by target following successful address decode.
0 = 0 to 33 MHz, 1 = 33 to 66 MHz.
Driven asserted by the CN8237 (as a bus slave) or by a
target addressed by the CN8237 when it acts as a bus
master to indicate a parity error on the HAD[32:63] and
HC/BE[3:0]* lines. It is asserted when the CN8237 is a bus
slave or sampled when the CN8237 is a bus master on the
second clock edge after a valid data phase. The CN8237
drives the HPERR* line only when acting as a slave.
Indicates a system error or a parity error on the
HAD[32:64] and HC/BE[3:0]* lines during an address
phase. This pin is handled in the same way as HPERR*,
and is only driven by the CN8237 when it acts as a bus
slave.
PCI bus clock signal.
Performs a hardware reset of the CN8237 and associated
peripherals when asserted. Must be asserted for 16 cycles
of HCLK.
Selects PCILITE mode. High = PCILITE mode (disables
retry disconnect).
Logic low means switch is locked, logic high means
switch is unlocked. Compact PCI hot swap signal. Must be
tied to ground if it is not used.
12 mA open drain. Logic low turns on LED. Compact PCI
hot swap signal.
8 mA open drain. Compact PCI hot swap signal.
Driven by master requesting 64-bit transfer.
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
2-31