CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 264

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

12.0 PCI Bus Interface
12.4 PCI Bus Master Logic
12-4
12.4 PCI Bus Master Logic
The PCI bus master logic block is responsible for accepting read and write
commands from the DMA coprocessor (passed via the burst FIFO buffers), and in
turn acquiring mastership of the PCI bus and generating transactions to perform
the actual data transfers. The bus master logic contains the following:
read or a write transfer, using the defined PCI protocol sequence. In this case, the
bus master logic terminates the current burst, maintain its bus request, and
restarts the transfer at the point of termination. Disconnects and retries are not
regarded as errors.
• A command decoder that interprets commands issued from the DMA
• A burst controller that counts off read and write cycles in each burst on the
• Arbitration logic that acquires control of the PCI bus.
• Supported arbitration parking.
• A bus state machine that sequences and controls transfers.
It is possible for the addressed slave to request a disconnect or a retry during a
coprocessor.
PCI bus (and also latches and drives the address and command during the
address phase of each transfer).
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237