CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 288

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

13.0 ATM UTOPIA Interface
13.9 Receive Cell Synchronization Logic
13-16
13.9 Receive Cell Synchronization Logic
The receive cell synchronization logic accepts a stream of octets (together with
error and cell boundary indications) from the receive ATM UTOPIA interface and
performs the following functions:
13.10 Transmit Cell Synchronization Logic
The transmit cell synchronization logic copies cell data from the transmit cell
FIFO buffer to the transmit ATM UTOPIA interface while performing the
following functions:
• Maintains a sequence counter that marks the various components of an
• Extracts and discards the HEC byte from each 53-byte ATM cell, leaving
• Formats consecutive 4-byte segments into 32-bit words; thus, the header
• Ensures that a complete cell (exactly 52 bytes) is always written to the
• Sets the RSM_OVFL bit in the HOST_ISTAT0 register if an octet could
• Reads 32-bit words from the transmit cell FIFO buffer and converts them
• Maintains a sequence counter that delineates the various components of
• Inserts a blank (all-0) HEC byte, used as a placeholder, into the outgoing
• Generates appropriate cell delineation pulses to the transmit ATM
• Sets the SEG_UNFL bit in the HOST_ISTAT0 register if the ATM
ATM cell: the 5-byte ATM header, the 1-byte HEC field within the header,
and the 48-byte payload. The sequence counter is also used by the ATM
UTOPIA interface to check cell boundary synchronization.
52 bytes of cell data.
forms the first word, the first four bytes of the payload form the next word,
and so on. A total of thirteen 32-bit words are created from each 52-byte
cell after the HEC byte has been removed. The bytes within each word are
left-justified (big-endian format), that is, the first byte received is the MSB
of the word.
FIFO buffer. If a synchronization error occurs, the FR_SYNC_ERR bit in
the HOST_ISTAT0 register is set. The ATM UTOPIA interface attempts to
resynchronize with the data stream.
not be transferred due to the receive FIFO buffer being full.
to a stream of octets, with the MSB of each 32-bit word corresponding to
the first byte derived from that word (big-endian format).
each ATM cell (4-byte header, 48-byte payload) in the outgoing byte
stream.
byte stream representing each ATM cell. The HEC placeholder is inserted
after the first four bytes (the ATM header) have been transferred.
UTOPIA interface logic, for use in generating the TxSOC (TxMARK)
output, and also in verifying synchronization with the framer device.
UTOPIA transmit interface runs out of cells to transmit.
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237