CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 364

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

16.0 Electrical and Mechanical Specifications
16.2 Package I/O Description
Figure 16-15. Interface Timing Diagram—Strobed Mode
16-16
PADATA[7:0] (read)
PDATA[7:0] (write)
PADDR[12:0]
PWAIT*
PWNR
PCLK
PCS*
PDS*
PAS*
Tas
in this diagram are the same as those in the previous normal mode timing
diagram. A single internally generated wait state is shown for illustrative
purposes.
Table 16-8. Interface Timing
16.2 Package I/O Description
The package interface (I/O) pins and descriptions are given in
normal mode, the PCS*, PAS*, PDS*, and PWNR pins are outputs providing chip
select, address strobe, data strobe and write/read control to the PHY device.
When the PDS* output is active, it indicates the cycles in which the data
transaction occurs. In strobed mode, PAS*, PDS*, and PWNR become address,
read and write strobes, respectively.
Tas
Twr
Tds
Tcs
NOTE(S):
Symbol
Timing for strobe mode is shown in
Write Address
address
Write Data
Other timing properties are the same as Normal Mode.
Mindspeed Technologies
All outputs are measured driving a 50 pF load.
PCLK fall to PAS* (ALE)
PCLK fall to PWNR (WRB)
PCLK fall to PDS* (RDB)
PCLK fall to PCS*
Twr
Tds
Tas
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Parameter
—
wait
Write Strobe
Read Strobe
Strobed Mode
Figure
™
16-15. Timing numbers not found
data
Read Data
Min
–4
–4
–4
–4
Tcs
Twr
Tds
Table
28237-DSH-001-C
Max
4
4
4
4
16-9. In
CN8237
Units
ns
ns
ns
ns
8237_128