CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 269

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
12.9.1 EEPROM Format
Table 12-1. EEPROM Fields
28237-DSH-001-C
0x00
0x01-0x03
0x04-0x05
0x06-0x07
0x08
0x09
0x0a
0x0b
NOTE(S):
(1)
Address
Do not set until after PCI Base Address register has been set.
Offset
FIELD_ENABLES
Reserved
SVID
SID
General Enables
Latency Timer
Memory Size Mask
PLL_MUL
Name
The first 32 bytes of the 128-byte EEPROM are used to store PCI configuration
information, loaded into the PCI Configuration space at reset. Unless otherwise
specified, all unused bytes are reserved and should be programmed to 0x00. Bytes
above address offset 0x20 can be used by application software or device drivers as
needed. The EEPROM fields are described in
Mindspeed Technologies
Bit 6: Load PLL_MUL from EEPROM
Bit 5: Load Memory Size Mask from EEPROM
Bit 4: Load Latency Timer from EEPROM
Bit 3: Load General Enables from EEPROM
Bit 2: Disable Capability registers (for Power Management)
Bit 1: Load Subsystem ID (SID) from EEPROM
Bit 0: Load Subsystem Vendor ID (SVID) from EEPROM
Set to 0s.
Subsystem Vendor ID.
Subsystem ID.
Bit 7: Special Status register Bit 26 (MSTR_CTRL_DWORD, Master Control
DWORD)
Bit 6: Special Status register Bit 27 (MSTR_DATA_DWORD, Master Data
DWORD)
Bit 5: Special Status register Bit 28 (SLAVE_DWORD, Slave DWORD)
Bit 4: Special Status register Bit 29 (SLAVE_SWAP, Slave Control Byte Swap)
Bit 3: Special Status register Bit 30 (MSTR_CTRL_SWAP, Master Control Byte
Swap)
Bit 2: PCI Command register Bit 6 (PE_EN, Enable Detection of Parity Errors)
Bit 1
Bit 0
Master Latency Timer
Valid Mask Values:
Bits 7–4: Reserved
Bits 3–0: PLL_MUL
Bit 7 6 5 4 3 2 1 0 = Size
(1)
(1)
: PCI Command register Bit 2 (M_EN, Master Enable)
: PCI Command register Bit 1 (MS_EN, Memory Space Enable)
0 0 0 0 0 0 0 0 = 16 M
1 0 0 0 0 0 0 0 = 8 M
Description
™
12.9 Interface Module to Serial EEPROM
Table
12-1.
12.0 PCI Bus Interface
12-9