CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 4

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

–Continued Distinguishing Features–
New Features
• 3.3 V, 456 BGA lowers power and
• 64-bit/66 MHz PCI 2.1, including
• Enhancements to xBR Traffic
• Reduced memory size for VCC
• Increased addressing flexibility
• Additional byte lane swappers for
• Programmable size routing tags up
• Selectable single/separate UTOPIA
• Updated PM-OAM processing per
• SECBC calculated per GR-1248
• Compact PCI Hot Swap capabilities
• Master PCI write over read arbitration
• Multi-PHY UTOPIA Level 2
• Head of line blocking protection for
xBR Traffic Management
• TM4.1 Service Classes
• 16 levels of priorities (16 + CBR)
• Dynamic per-VCC scheduling
• Multiple programmable ABR
• Scheduler driven by selectable clock
• Internal RM OAM cell feedback path
• Virtual FIFO buffer rate matching
• Per-VCC MCR and ICR
• Tunneling
28237-DSH-001-C
eases PCB assembly
support for serial EEPROM
Manager
– fewer ABR templates
– improved CBR tunneling
lookup tables
increased system flexibility
to 64 B cells
clocks
i.610
control
multi-PHY operation
– CBR
– VBR (single, dual and CLP-based
– Real time VBR
– ABR (ER, RR, EFCI)
– UBR
– GFC (controlled and uncontrolled
– Guaranteed Frame Rate (GFR)
templates (supplied by Mindspeed
or user)
– Local system clock
– External reference clock
(Source Rate Matching)
– VP tunnels (VCI interleaving on
– CBR tunnels (cells interleaved as
leaky buckets)
flows)
(guaranteed MCR on UBR VCCs)
PDU boundaries)
UBR, VBR, or ABR with an
aggregate CBR limit)
Multi-Queue Segmentation Processing
• 32 transmit queues with optional
• 64 K VCCs maximum
• AAL5 CPCS generation
• AAL0 Null CPCS (optional use of PTI
• ATM cell header generation
• Raw cell mode (52 octet)
• 800 Mbps half duplex
• 622 Mbps full duplex (w/ 2-cell
• Variable length transmit FIFO buffer -
• Symmetric Tx and Rx architecture
• User defined field circulates back to
• Distributed host or SAR-shared
• Simultaneous segmentation and
• Per-PDU control of CLP/PTI (UBR)
• Per-PDU control of AAL5 UU field
• Message and streaming status
• Virtual Tx FIFO buffer (PCI host)
Multi-Queue Reassembly Processing
• 32 reassembly queues
• 64 K VCCs maximum
• AAL5 CPCS checking
• AAL0
• Early Packet Discard, based on:
• Dynamic channel lookup (NNI or UNI
• Message and streaming status
• Raw cell mode (52 octet)
• 800 Mbps half duplex
Mindspeed Technologies
priority levels
for PDU demarcation)
PDUs)
CDV - host latency matching (1 to 9
cells)
– buffer descriptors
– queues
the host (32 bits)
memory segmentation
reassembly
modes
– PTI termination
– Cell count termination
– Receive buffer underflow
– Receive status overflow
– CLP with priority threshold
– AAL5 max PDU length
– Rx FIFO buffer full
– Frame relay DE with priority
– LECID filtering and echo
– Per-VCC firewalls
addressing)
– Supports full address space
– Deterministic
– Flexible VCI count per VPI
– Optimized for signalling address
modes
threshold
suppression
assignment
™
• 622 Mbps full duplex (with 2-cell
• Distributed host or SAR-shared
• 8 programmable reassembly
• Global max PDU length for AAL5
• Per-VCC buffer firewall (memory
• Simultaneous reassembly and
• Idle cell filtering
• 64 K duplex VCCs
High Performance Host Architecture
with Buffer Isolation
• Write-only control and status
• Read multiple command for data
• Up to 32 host clients control and
• Physical or logical clients
• Descriptor-based buffer chaining
• Scatter/gather DMA
• Endian neutral (allows data word and
• Non-word (byte) aligned host buffer
• Automatically detects presence of Tx
• Virtual FIFO buffers (PCI bursts
• Hardware indication of BOM
• Allows isolation of system resources
• Status queue interrupt delay
Designer Toolkit
• Evaluation hardware and software
• Reference schematics
• Hardware Programming
Generous Implementation of OAM-PM
Protocols
• Detection of all F4/F5 OAM flows
• Internal PM monitoring and
• Optional global OAM Rx/Tx queues
• In-line OAM insertion and generation
–Continued–
PDUs)
memory reassembly
hardware time-outs (per-VCC
assignable)
usage limit)
segmentation
transfer
status queues
– Enables peer-to-peer architecture
control word byte swapping, for both
big and little endian systems)
addresses
data or Rx free buffers
treated as a single address)
Interface-RS823xHPI reference
source code (C)
generation for up to 128 VCCs