XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 154

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Standard Timer Module (TIM)
12.3.7 Timer Control Registers
Data Sheet
154
NOTE:
TSWAI — Timer Stops While in Wait Bit
TSBCK — Timer Stops While in Background Mode Bit
TFFCA — Timer Fast Flag Clear All Bit
Extra care is required to avoid accidental flag clearing due to unintended accesses.
Read: Anytime
Write: Anytime
OMn — Output mode
OLn — Output level
Address: $0088
Address: $0089
Timer interrupts cannot be used to get the MCU out of wait.
These eight pairs of control bits are encoded to specify the output action to be
taken as a result of a successful OCn compare (see
OMn or OLn is 1, the pin associated with OCn becomes an output tied to OCn
regardless of the state of the associated DDRT bit.
Reset:
Reset:
Read:
Read:
Write:
Write:
0 = Allows timer to continue running during wait
1 = Disables timer when MCU is in wait mode
0 = Allows timer to continue running while in background mode
1 = Disables timer when MCU is in background mode; useful for emulation
0 = Allows timer flag clearing to function normally
1 = For TFLG1($8E), a read from an input capture or a write to the output
compare channel ($90–$9F) causes the corresponding channel flag,
CnF, to be cleared. For TFLG2 ($8F), any access to the TCNT register
($84, $85) clears the TOF flag. Any access to the PACNT register ($A2
and $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1).
This has the advantage of eliminating software overhead in a separate
clear sequence.
OM7
OM3
Bit 7
Bit 7
0
0
Figure 12-8. Timer Control Register 1 (TCTL1)
Figure 12-9. Timer Control Register 2 (TCTL2)
Standard Timer Module (TIM)
OL7
OL3
6
0
6
0
OM6
OM2
5
0
5
0
OL6
OL2
4
0
4
0
OM5
OM1
3
0
3
0
Table
M68HC12B Family — Rev. 8.0
OL5
OL1
2
0
2
0
12-1). When either
OM4
OM0
1
0
1
0
MOTOROLA
Bit 0
Bit 0
OL4
OL0
0
0