XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 246

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.8.2 Rx and Tx Shift Registers
15.8.3 Rx and Tx Shadow Registers
15.8.4 Digital Loopback Multiplexer
15.8.5 State Machine
15.8.5.1 4X Mode
15.8.5.2 Receiving a Message in Block Mode
Data Sheet
246
The Rx shift register gathers received serial data bits from the J1850 bus and
makes them available in parallel form to the Rx shadow register. The Tx shift
register takes data, in parallel form, from the Tx shadow register and presents it
serially to the state machine so that it can be transmitted onto the J1850 bus.
Immediately after the Rx shift register has completed shifting in a byte of data, this
data is transferred to the Rx shadow register and RDRF or RXIFR is set (see
BDLC State Vector
(IE) in BCR1 is set. After the transfer takes place, this new data byte in the Rx
shadow register is available to the CPU interface, and the Rx shift register is ready
to shift in the next byte of data. Data in the Rx shadow register must be retrieved
by the CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the current byte,
the data byte in the Tx shadow register is loaded into the Tx shift register. After this
transfer takes place, the Tx shadow register is ready to accept new data from the
CPU when the TDRE flag in the BSVR is set.
The digital loopback multiplexer connects RxD to either BDTxD or BDRxD,
depending on the state of the DLOOP bit in the BCR2. (See
Register
All functions associated with performing the protocol are executed or controlled by
the state machine. The state machine is responsible for framing, collision
detection, arbitration, CRC generation/checking, and error detection. These
sections describe the BDLC’s actions in a variety of situations.
The BDLC can exist on the same J1850 bus as modules which use a special 4X
(41.6 Kbps) mode of J1850 variable pulse width modulation (VPW) operation. The
BDLC cannot transmit in 4X mode, but it can receive messages in 4X mode, if the
RX4X bit is set in BCR2. If the RX4X bit is not set in the BCR2, any 4X message
on the J1850 bus is treated as noise by the BDLC and is ignored.
Although not a part of the SAE J1850 protocol, the BDLC does allow for a special
block mode of operation of the receiver. As far as the BDLC is concerned, a block
mode message is simply a long J1850 frame that contains an indefinite number of
2.)
Byte Data Link Communications (BDLC)
Register). An interrupt is generated if the interrupt enable bit
M68HC12B Family — Rev. 8.0
15.9.2 BDLC Control
MOTOROLA
15.9.3