XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 73

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

4.5.2 Highest Priority I Interrupt Register
4.6 Resets
4.6.1 Power-On Reset (POR)
4.6.2 External Reset
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Only if I bit in CCR = 1 (interrupts inhibited)
To give a maskable interrupt source highest priority, write the low byte of the vector
address to the HPRIO register. For example, writing $F0 to HPRIO assigns highest
maskable interrupt priority to the real-time interrupt timer ($FFF0). If an
unimplemented vector address or a non-I-masked vector address (a value higher
than $F2) is written, then IRQ is the default highest priority interrupt.
There are four possible sources of reset. POR and external reset on the RESET
pin share the normal reset vector. COP reset and the clock monitor reset each has
a vector. Entry into reset is asynchronous and does not require a clock, but the
MCU cannot sequence out of reset without a system clock.
A positive transition on V
other external reset circuits are the usual source of reset in a system. The POR
circuit only initializes internal circuitry during cold starts and cannot be used to force
a reset as system voltage drops.
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic 1 in less than eight E-clock cycles after an
internal device releases reset. When a reset condition is sensed, the RESET pin is
driven low by an internal device for about 16 E-clock cycles, then released. Eight
E-clock cycles later it is sampled. If the pin is still held low, the CPU assumes that
an external reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
To prevent a COP or clock monitor reset from being detected during an external
reset, hold the reset pin low for at least 32 cycles. An external resistor-capacitor
(RC) power-up delay circuit on the reset pin is not recommended because circuit
charge time can cause the MCU to misinterpret the type of reset that has occurred.
Address:
Reset:
Read:
Write:
Figure 4-2. Highest Priority I Interrupt Register (HPRIO)
$001F
Bit 7
1
1
Resets and Interrupts
6
1
1
DD
causes a POR. An external voltage level detector or
PSEL5
5
1
PSEL4
4
1
PSEL3
3
0
PSEL2
2
0
Resets and Interrupts
PSEL1
1
1
Data Sheet
Bit 0
Resets
0
0
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