XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 331
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
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M68HC12B Family — Rev. 8.0
MOTOROLA
BKMBL — Breakpoint Mask Low Bit
BK1RWE — R/W Compare Enable Bit
BK1RW — R/W Compare Value Bit
BK0RWE — R/W Compare Enable Bit
BK0RW — R/W Compare Value Bit
BK1RWE BK1RW BK0RWE BK0RW
Disables the matching of the low byte of data when in full breakpoint mode.
Used in conjunction with the BKDBE bit (which should be set)
Enables the comparison of the R/W signal to further specify what causes a
match. This bit is NOT useful in program breakpoints or in full breakpoint mode.
This bit is used in conjunction with a second address in dual address mode
when BKDBE = 1.
When BK1RWE = 1, this bit determines the type of bus cycle to match.
Enables the comparison of the R/W signal to further specify what causes a
match. This bit is not useful in program breakpoints.
When BK0RWE = 1, this bit determines the type of bus cycle to match.
—
—
—
0
1
1
0 = Low byte of data bus (bits 7–0) are compared to BRKDL.
1 = Low byte is not used to in comparisons.
0 = R/W is not used in comparisons.
1 = R/W is used in comparisons.
0 = A write cycle is matched.
1 = A read cycle is matched.
0 = R/W is not used in the comparisons.
1 = R/W is used in comparisons.
0 = Write cycle is matched.
1 = Read cycle is matched.
—
—
—
X
0
1
Table 18-9. Breakpoint Read/Write Control
Development Support
—
—
—
0
1
1
—
—
—
X
0
1
R/W is don’t care for full mode or dual mode BKP0
R/W is write for full mode or dual mode BKP0
R/W is read for full mode or dual mode BKP0
R/W is don’t care for dual mode BKP1
R/W is write for dual mode BKP1
R/W is read for dual mode BKP1
Read/Write Selected
Development Support
Breakpoints
Data Sheet
331
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