XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 193

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

13.4.16 Input Control Pulse Accumulators Control Register
13.4.17 Delay Counter Control Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime
The 8-bit pulse accumulators, PAC3 and PAC2, can be enabled only if PAEN in
PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN have no effect. The
8-bit pulse accumulators, PAC1 and PAC0, can be enabled only if PBEN in PBTCL
($B0) is cleared. If PBEN is set, PA1EN and PA0EN have no effect.
PAxEN — 8-Bit Pulse Accumulator x Enable Bits
Read: Anytime
Write: Anytime
If enabled, after detection of a valid edge on input capture pin, the delay counter
counts the pre-selected number of P clock (module clock) cycles, then it will
generate a pulse on its output. The pulse is generated only if the level of input
signal, after the preset delay, is the opposite of the level before the transition.This
will avoid reaction to narrow input pulses.
After counting, the counter will be cleared automatically. Delay between two active
edges of the input signal period should be longer than the selected counter delay.
DLYx — Delay Counter Select Bits
Figure 13-37. Input Control Pulse Accumulators Control Register (ICPACR)
Address: $00A8
Address: $00A9
Reset:
Reset:
Read:
Read:
Write:
Write:
0 = 8-bit pulse accumulator disabled
1 = 8-bit pulse accumulator enabled
DLY1
0
0
1
1
Figure 13-38. Delay Counter Control Register (DLYCT)
Bit 7
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
0
0
DLY0
0
1
0
1
6
0
0
6
0
0
Disabled (bypassed)
256 P clock cycles
512 P clock cycles
1024 P clock cycles
5
0
0
5
0
0
Delay
4
0
0
4
0
0
Enhanced Capture Timer (ECT) Module
PA3EN
3
0
3
0
0
PA2EN
2
0
2
0
0
PA1EN
DLY1
Timer Registers
1
0
1
0
Data Sheet
PA0EN
DLY0
Bit 0
Bit 0
0
0
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