XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 197

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

13.4.22 Data Direction Register for Timer Port
13.4.23 16-Bit Pulse Accumulator B Control Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime
DDT[7:0] — Data Direction Bits for Timer Port
Read: Anytime
Write: Anytime
Sixteen-bit pulse accumulator B (PACB) is formed by cascading the 8-bit pulse
accumulators PAC1 and PAC0. When PBEN is set, the PACB is enabled. The
PACB shares the input pin with IC0.
PBEN — Pulse Accumulator B System Enable Bit
The timer forces the I/O state to be an output for each timer port line associated
with an enabled output compare. In these cases the data direction bits will not
be changed, but have no effect on the direction of these pins. The DDRT will
revert to controlling the I/O direction of a pin when the associated timer output
compare is disabled. Input captures do not override the DDRT settings.
PBEN is independent from TEN. With timer disabled, the pulse accumulator can
still function unless pulse accumulator is disabled.
Address: $00AF
Address: $00B0
Reset:
Reset:
Figure 13-44. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Read:
Read:
Write:
Write:
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
0 = 16-bit pulse accumulator system disabled. Eight-bit PAC1 and PAC0 can
1 = Pulse accumulator B system enabled. The two 8-bit pulse accumulators
Figure 13-43. Data Direction Register for Timer Port (DDRT)
be enabled when their related enable bits in ICPACR ($A8) are set.
PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB is enabled, the PACN1 and PACN0 register
contents are, respectively, the high and low byte of the PACB. PA1EN
and PA0EN control bits in ICPACR ($A8) have no effect.
DDT7
Bit 7
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
0
PBEN
DDT6
6
0
6
0
DDT5
5
0
5
0
0
DDT4
4
0
4
0
0
Enhanced Capture Timer (ECT) Module
DDT3
3
0
3
0
0
DDT2
2
0
2
0
0
PBOV
DDT1
Timer Registers
1
0
1
0
Data Sheet
DDT0
Bit 0
Bit 0
0
0
0
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