XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 66

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XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
Central Processor Unit (CPU)
3.5 Addressing Modes
Data Sheet
66
auto post-increment
auto pre-decrement
Addressing Mode
auto pre-increment
accumulator offset
Indexed-Indirect
Indexed-Indirect
D accumulator
16-bit offset
16-bit offset
Immediate
5-bit offset
decrement
9-bit offset
auto post-
Extended
Inherent
Relative
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Indexed
Direct
offset
Addressing modes determine how the CPU accesses memory locations to be
operated upon. The CPU12 includes all of the addressing modes of the M68HC11
CPU as well as several new forms of indexed addressing.
of the available addressing modes.
INST [oprx16,xysp]
INST oprx16,xysp
INST oprx5,xysp
INST oprx3,–xys
INST oprx3,+xys
INST oprx3,xys–
INST oprx3,xys+
INST oprx9,xysp
Source Format
INST abd,xysp
INST [D,xysp]
INST #opr16i
INST opr16a
INST #opr8i
INST opr8a
INST rel16
INST rel8
INST
or
or
Table 3-1. Addressing Mode Summary
Central Processor Unit (CPU)
Abbreviation
[D,IDX]
[IDX2]
IDX1
IDX2
IMM
EXT
REL
INH
DIR
IDX
IDX
IDX
IDX
IDX
IDX
Operand is a 16-bit address.
5-bit signed constant offset from x, y, sp, or pc
Auto pre-decrement x, y, or sp by 1 ~ 8
Auto pre-increment x, y, or sp by 1 ~ 8
Auto post-decrement x, y, or sp by 1 ~ 8
Auto post-increment x, y, or sp by 1 ~ 8
Indexed with 8-bit (A or B) or 16-bit (D) accumulator
offset from x, y, sp, or pc
9-bit signed constant offset from x, y, sp, or pc
(lower 8 bits of offset in one extension byte)
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Pointer to operand is found at
16-bit constant offset from x, y, sp, or pc
(16-bit offset in two extension bytes)
Pointer to operand is found at
x, y, sp, or pc plus the value in D
Operands (if any) are in CPU registers.
Operand is included in instruction stream
8- or 16-bit size implied by context.
Operand is the lower 8 bits of an address in the range
$0000–$00FF.
An 8-bit or 16-bit relative offset from the current pc is
supplied in the instruction.
Description
M68HC12B Family — Rev. 8.0
Table 3-1
is a summary
MOTOROLA

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