XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 75

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

4.7.4 Parallel Input/Output (I/O)
4.7.5 Central Processing Unit (CPU)
4.7.6 Memory
4.7.7 Other Resources
4.8 Interrupt Recognition
M68HC12B Family — Rev. 8.0
MOTOROLA
If the MCU comes out of reset in an expanded mode, port A and port B are the
multiplexed address/data bus. Port E pins are normally used to control the external
bus. The port E assignment register (PEAR) affects port E pin operation.
If the MCU comes out of reset in a single-chip mode, all ports are configured as
general-purpose high-impedance inputs.
After reset, the CPU fetches a vector from the appropriate address and begins
executing instructions. The stack pointer and other CPU registers are
indeterminate immediately after reset. The condition code register (CCR) X and I
interrupt mask bits are set to mask any interrupt requests. The S bit is also set to
inhibit the STOP instruction.
After reset, the internal register block is located at $0000–$01FF, the
register-following space is at $0200–$03FF, and RAM is at $0800–$0BFF.
EEPROM is located at $0D00–$0FFF. FLASH EEPROM/ROM is located at
$8000–$FFFF in single-chip modes and at $0000–$7FFF (but disabled) in
expanded modes.
The timer, serial communications interface (SCI), serial peripheral interface (SPI),
byte data link controller (BDLC), pulse-width modulator (PWM), analog-to-digital
converter (ATD), and Motorola scalable controller area network (MSCAN) are off
after reset.
Once enabled, an interrupt request can be recognized at any time after the I bit in
the CCR is cleared. When an interrupt request is recognized, the CPU responds at
the completion of the instruction being executed. Interrupt latency varies according
to the number of cycles required to complete the instruction. Some of the longer
instructions can be interrupted and resume normally after servicing the interrupt.
When the CPU begins to service an interrupt request, it:
•
•
•
Clears the instruction queue
Calculates the return address
Stacks the return address and the contents of the CPU registers as shown
in
Table 4-3
Resets and Interrupts
Resets and Interrupts
Interrupt Recognition
Data Sheet
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