XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 190

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Enhanced Capture Timer (ECT) Module
13.4.13 Pulse Accumulators Count Registers
Data Sheet
190
Read: Anytime
Write: Anytime
The two 8-bit pulse accumulators, PAC3 and PAC2, are cascaded to form the
PACA 16-bit pulse accumulator. When PACA in enabled (PAEN = 1 in PACTL,
$A0) the PACN3 and PACN2 registers’ contents are, respectively, the high and low
bytes of the PACA.
When PACN3 overflows from $FF to $00, the interrupt flag PAOVF in PAFLG ($A1)
is set. Full count register access should take place in one clock cycle. A separate
read/write for high byte and low byte will give a different result than accessing them
as a word.
Read: Anytime
Write: Anytime
Address: $00A2
Address: $00A3
Address: $00A4
Address: $00A5
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 13-31. Pulse Accumulator Count Register 3 (PACN3)
Figure 13-32. Pulse Accumulator Count Register 2 (PACN2)
Figure 13-33. Pulse Accumulator Count Register 1 (PACN1)
Figure 13-34. Pulse Accumulator Count Register 0 (PACN0)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
0
0
Bit 6
Bit 6
Bit 6
Bit 6
6
0
6
0
6
0
6
0
Bit 5
Bit 5
Bit 5
Bit 5
5
0
5
0
5
0
5
0
Bit 4
Bit 4
Bit 4
Bit 4
4
0
4
0
4
0
4
0
Bit 3
Bit 3
Bit 3
Bit 3
3
0
3
0
3
0
3
0
M68HC12B Family — Rev. 8.0
Bit 2
Bit 2
Bit 2
Bit 2
2
0
2
0
2
0
2
0
Bit 1
Bit 1
Bit 1
Bit 1
1
0
1
0
1
0
1
0
MOTOROLA
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0