XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 255

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
TMIFR1 — Transmit Multiple Byte IFR with CRC Bit (Type 3)
The extra logic 1 bits are an enhancement to the J1850 protocol which forces a
byte boundary condition fault. This is helpful in preventing noise on the J1850 bus
from corrupting a message.
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC data
register (BDR) as the first byte of a multiple byte IFR with CRC or as a single
byte IFR with CRC. Response IFR bytes are still subject to J1850 message
length maximums (see
If the TMIFR1 bit is set, the BDLC attempts to transmit the normalization symbol
followed by the byte in the BDR. After the byte in the BDR has been loaded into
the transmit shift register, a TDRE interrupt (see
Register) occurs similar to the main message transmit sequence. The
programmer should then load the next byte of the IFR into the BDR for
transmission. When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BDLC control register 2 (BCR2).
This instructs the BDLC to transmit a CRC byte once the byte in the BDR is
transmitted, and then transmit an EOD symbol, indicating the end of the IFR
portion of the message frame.
However, to transmit a single byte followed by a CRC byte, the programmer
should load the byte into the BDR before the EOD symbol has been received,
and then set the TMIFR1 bit. Once the TDRE interrupt occurs, the programmer
sets the TEOD bit in the BCR2. This results in the byte in the BDR being the only
byte transmitted before the IFR CRC byte, and no TDRE interrupt is generated.
If the programmer attempts to set the TMIFR1 bit immediately after the EOD
symbol has been received from the bus, the TMIFR1 bit remains in the reset
state, and no attempt is made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting any byte of a
multiple byte IFR, the BDLC goes to the loss of arbitration state, sets the
appropriate flag, and ceases transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit is cleared and no
attempt is made to retransmit the byte in the BDR. If loss of arbitration occurs in
the last bit of the IFR byte, two additional 1 bits are sent out.
1 = If this bit is set prior to a valid EOD being received with no CRC error,
0 = The bit is cleared automatically, once the BDLC has successfully
once the EOD symbol has been received, the BDLC attempts to transmit
the appropriate normalization bit followed by IFR bytes. The
programmer should set TEOD after the last IFR byte has been written
into the BDR. After TEOD has been set and the last IFR byte has been
transmitted, the CRC byte is transmitted.
transmitted the CRC byte and EOD symbol, by the detection of an error
on the multiplex bus or by a transmitter underrun caused when the
programmer does not write another byte to the BDR after the TDRE
interrupt.
Byte Data Link Communications (BDLC)
15.7.2 J1850 Frame Format
Byte Data Link Communications (BDLC)
15.9.3 BDLC State Vector
and
Figure
BDLC Registers
15-14).
Data Sheet
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