XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 297

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

16.12.13 msCAN12 Identifier Mask Registers
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
AC7–AC0 — Acceptance Code Bits
The CIDAR0-CIDAR7 registers can be written only if the SFTRES bit in CMCR0 is
set.
The identifier mask register specifies which of the corresponding bits in the
identifier acceptance register are relevant for acceptance filtering. To receive
standard identifiers in 32-bit filter mode, the last three bits (AM2–AM0) in the mask
registers CIDMR1 and CIDMR5 must be programmed to don’t care. To receive
standard identifiers in 16 bit filter mode the last three bits (AM2–AM0) in the mask
registers CIDMR1, CIDMR3, CIDMR5, and CIDMR7 must be programmed to don’t
care.
AC7–AC0 comprise a user-defined sequence of bits with which the
corresponding bits of the related identifier register (IDRn) of the receive
message buffer are compared. The result of this comparison is then masked
with the corresponding identifier mask register.
Address: $0114
Address: $0115
Address: $0116
Address: $0117
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
AM7
AM7
AM7
AM7
Bit 7
Bit 7
Bit 7
Bit 7
Figure 16-29. First Bank msCAN12 Identifier Mask
msCAN12 Controller
AM6
AM6
AM6
AM6
6
6
6
6
Registers (CIDMR0–CIDMR3)
AM5
AM5
AM5
AM5
5
5
5
5
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AM4
AM4
AM4
AM4
4
4
4
4
Programmer’s Model of Control Registers
AM3
AM3
AM3
AM3
3
3
3
3
AM2
AM2
AM2
AM2
2
2
2
2
msCAN12 Controller
AM1
AM1
AM1
AM1
1
1
1
1
Data Sheet
AM0
AM0
AM0
AM0
Bit 0
Bit 0
Bit 0
Bit 0
297