mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 11

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

0 to 7, respectively. For example, if only two DSo channels, 0 and 2 on stream 0, are enabled then the
corresponding channels 0 and 2 on FGA4 will be pulled low and the remaining channels will be left high. Similarly,
FGB4 to FGB11 outputs correspond to output drive enables for the MVIP DSi channels within streams 0 to 7,
respectively.
In mode 2, frame groups A&B are programmed as output framing pulses for use with the local serial data streams
(refer to Figure 16 - “Frame Pulse Timing for Mode 2” for further details). The position of the first framing signal in a
group is determined by an 11 bit quantity. The quantity is the FMIC state number (the number of 16 MHz clock
cycles during one frame) minus one. The lower eight bits of this quantity are located in the frame start register, and
the upper three bits are located in the frame mode register.The width of the framing signal is determined by the
state of the FRM_TYPE bit in the frame mode register and can be either a single bit cell time or 8 bit cell times. All
framing signals in the same group (A or B) follow each other sequentially, that is, the first FGx[0] is asserted then
exactly 8 bit cell times later FGx[1] is asserted and so on until the last framing signal in the group is asserted. The
distance between consecutive frame pulses within a frame group can be one 2, 4 or 8 Mb/s channel time and can
be specified by two bits in the frame mode register.
Mode 3 is identical to mode 2 except the polarity of the framing pulses is logically inverted.
Refer to Tables 13 to 16 for details on the frame start and frame mode registers.
All the framing signals FGA[0:11] and FGB[0:11] are available in the 100 pin PQFP package.
Delay through the MT90810
Switching delay through the FMIC is dependent on input and output stream, source and destination channel, as
well as, I/O data rate. A summary of throughput delay values for the device is provided in Table 1, “Throughput
Delay Values”. The minimum delay achievable in the MT90810 depends on the data rate selected for the streams.
When switching from a slower input data rate to a faster output data rate, the minimum delay is set by the faster
output data rate and the maximum delay is set by the slower input data rate. When switching from a faster input
data rate to a slower output data rate, the minimum delay is set by the slower output data rate and the maximum
delay is set by the faster input data rate.
2.048 - 2.048 Mb/s
4.096 - 4.096 Mb/s
8.192 - 8.192 Mb/s
2.048 - 4.096 Mb/s
2.048 - 8.192 Mb/s
4.096 - 2.048 Mb/s
8.192 - 2.048 Mb/s
Input - Output
t.s.=timeslot is used synonymously with channel
fr.=125 µs frame
2 Mb/s t.s.=3.9 µs
4 Mb/s t.s.=1.95 µs
8 Mb/s t.s.=0.975 µs
Rate
Table 1 - Throughput Delay Values
Zarlink Semiconductor Inc.
5 x 8 Mb/s t.s.
2 x 2 Mb/s t.s.
2 x 2 Mb/s t.s.
3 x 4 Mb/s t.s.
3 x 4 Mb/s t.s.
5 x 8 Mb/s t.s.
2 x 2 Mb/s t.s.
MT90810
min
11
Throughput Delay
1 fr. + 2 x 2 Mb/s t.s.
1 fr. + 5 x 4 Mb/s t.s.
1 fr. + 11 x 8 Mb/s t.s.
1 fr. + 2 x 2 Mb/s t.s.
1 fr. + 2 x 2 Mb/s t.s.
1 fr. + 5 x 4 Mb/s t.s.
1 fr. + 11 x 8 Mb/s t.s.
max
Data Sheet