mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 8

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

The operation of the PLLs and the state machine is controlled by the clock control register as described in Figure 6
- “Clock Control (CLK_CNTRL) Register” and Tables 8 to 10. The clock circuitry (PLLs and state machine) operates
in eight different modes.
1. FMIC as Timing Master (Mode 0)
The FMIC is configured as the timing master (CLK_CNTRL register cleared, PLL mode 0 selected) after reset. The
external 16.384 MHz input is divided by four and used as the input to the analog PLL so the internal master clock is
phase locked to the 16.384 MHz oscillator. The FMIC state machine is free-running and does not synchronize to
any external 8 kHz source.
In this mode, the XLCK_SEL bits of the clock control register can be programmed to accommodate an 8.192 MHz
or 4.096 MHz external clock instead of the default 16.384 MHz.
The FMIC becomes MVIP master when MVIP_MST bit is set in the Control/Status register. This mode can be used
when the FMIC chip is to become timing master in a system which has no digital network connections (T1 or E1).
2. FMIC as MVIP Slave (Mode 4)
When this mode is selected, MVIP C4 clock is selected as the input to the analog PLL. The FMIC internal master
clock is then synchronized to the MVIP bus timing. The FMIC state machine is also synchronized to the MVIP F0
framing signal.
The MVIP_MST bit in the Control/Status register should never be set when the device is in mode 4 as the FMIC is
entirely slave to the MVIP bus timing.
3. FMIC as MVIP Master (Mode 1,2,3)
In modes 1 through 3, the output of the device’s digital PLL is selected as the input to the analog PLL. The source
to the digital PLL is selected as either SEC8K, EX_8KA or EX_8KB depending on the particular mode (1, 2 or 3)
chosen.
In these modes, the FMIC state machine is not synchronized to the external 8 kHz input selected, that is, the state
machine output 8 kHz FRAME and F0b signals may not be phase aligned with the external 8 kHz input but will
always be frequency locked.
C4b
16MHz Crystal
F0b
External
EX_8KA
EX_8KB
X1
X2
div 4
div 2
0
0
1
2, 6
Figure 4 - Clock Control Functional Block Diagram
XCLK_SEL
1, 5
16MHz
PLL_MODE
4
2
3, 7
SEC8K
PLL_MODE
External 8kHz
Zarlink Semiconductor Inc.
MT90810
(sampler)
Digital
Jittery 4.096MHz
PLL
60ns peak jitter
8kHz
8
machine
FMIC
state
div 4
EX_8KA
EX_8KB
FRAME
4.096MHz
16MHz
1
by 2
Comparator
div
F0b
Analog PLL
FRAME
C4b
CLK8
CLK4
C2o
CLK2
0
Phase
2
SEL_S8K
@32MHz
VCO
EN_SEC8K
up/
down
PLL_LI
PLL_LO
Data Sheet
external
loop
filter
SEC8K