mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 5

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

Device Overview
Zarlink’s MT90810 is a MVIP compliant device. It provides a complete, cost effective, MVIP compliant interface
between the MVIP Bus and a wide variety of processors, telephony interfaces and other circuits. The FMIC
supports 384 full duplex, time division multiplexed (TDM), channels. These channels are divided into 256 full duplex
MVIP channels and 128 full duplex local channels. The sample rate for each channel is 8 kHz and the width of each
channel is 8 bits for a total data rate of 64 kbits/s per channel.
The FMIC’s internal clock circuitry includes both an analog and a digital PLL and supports all MVIP clock modes.
The device can be configured as a timing master whereby an external 16.384 MHz crystal or 4.096, 8.192 or
16.384 MHz external clock source is used to generate MVIP clock signals. The device can also operate as a slave
to the MVIP bus, synchronizing its master clock to the MVIP 4 MHz bus clock.
The device’s local serial interface supports PCM rates of 2.048, 4.096 and 8.192 Mb/s, per channel message
mode, an additional control stream, as well as parallel DMA through the microprocessor port. Furthermore, the
FMIC’s programmable group of output framing signals and local output clocks may be used to provide the
appropriate frame and clock pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and writing of the data memory, connection memory and all internal
control registers. The Connection and Data memory can be read and updated while the MVIP bus is active, that is,
connections can be made without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any input channel to any output channel. This is accomplished by
buffering a single sample of each channel in an on-chip 384 byte static RAM. Samples are written into this data
RAM in a fixed order and read out in an order determined by the programming of the connection memory. An input
shift register and holding latch for each input stream make up the serial to parallel conversion blocks on the input of
Pin Description (continued)
15, 40,
16, 41,
52, 66,
65, 86
79, 93
Pin #
12
13
17
18
22
23
21
24
X1/CLKIN
VCO_VD
VCO_VS
VDD[0:3]
VSS[0:5]
PLL_LO
PLL_LI
Name
TDO
TMS
X2
D
S
JTAG Serial Output Data (Output). If not used, this pin should be left unconnected.
JTAG Mode Control Input (TTL Input). If not used, this pin should be left unconnected.
Clock Input Pin/ Crystal Oscillator Pin1.
Crystal Oscillator Pin 2 (Input). If X1 is clock input, this pin should be left
unconnected.
PLL Loop Filter Output. (Output 6 mA drive).
PLL Loop Filter Input. (1 µA Low level/High level Input current).
Ground for On-chip VCO.
+5 Volt Power Supply for On-chip VCO.
Ground.
+5 Volt Power Supply.
Zarlink Semiconductor Inc.
MT90810
5
Description
Data Sheet