mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 21

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

7:3
2
1
0
Frame Start (FRMx_STRT) Register x
Frame Mode (FRMx_STRT) Register x
Bit
Bit
7:0
7:6
4:3
2:0
5
MVIP Stream 0
MVIP Stream 1
MVIP Stream 2
MVIP Stream 3
MVIP Stream 4
MVIP Stream 5
MVIP Stream 6
MVIP Stream 7
Local Stream 0
Local Stream 1
Streams
RESERVED
VCO_BYP
RESERVED
SEL_XIN
STRT(7:0)
MODE
FRM_TYPE
BIT_RATE
STRT(11:8)
Name
Name
Table 16 - Frame Register Bits for modes 2 & 3
Should NEVER be set under normal operating conditions
Bypass On-chip VCO
External VCO may be used in place of FMIC VCO
Should NEVER be set under normal operating conditions
Select X1 as chip master clock, direct input to FMIC state machine.
Bypass entire On-chip APLL (including VCO)
Table 17 - Diagnostic (DIAG_REG) Register
Table 18 - Data Memory Mapping
Lower 8 bits of the 11 bit quantity specified in Table 13 - “Frame Group
Mode bits”
Frame Group Mode
2 [10] Normal Framing
3 [11] Inverted Framing
Type of framing signal for this group
0 Frame pulse is one bit cell wide
1 Frame pulse is eight bit cell wide
Frame Group bit rate register
Spacing for the framing pulses is for:
0 [00] 2 Mb/s data rate
1 [01] 4 Mb/s data rate
2 [10] 8 Mb/s data rate
3 [11] Reserved
Upper three bits of the 11 bit quantity specified in Table 13 - “Frame Group
Mode bits”
Channels
0:31
0:31
0:31
0:31
0:31
0:31
0:31
0:31
0:31
0:31
Zarlink Semiconductor Inc.
MT90810
21
Description
decimal
128:159
160:191
192:223
224:255
256:287
288:319
96:127
32:63
64:95
0:31
Description
Indirect RAM Address
0x120:0x13f
0x100:0x11f
0x00:0x1f
0x20:0x3f
0x40:0x5f
0x60:0x7f
0x80:0x9f
0xa0:0xbf
0xc0:0xdf
0xe0:0xff
hex
Data Sheet