mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 14

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

If a DMA read or write request is not completely served by the time the next request needs to be asserted, a DMA
overrun error occurs. This causes the corresponding overrun bit in the MCS register, as well as, the ERR bit to be
set. DMA access can be throttled by disabling DMA for several timeslots in between channels that have DMA
enabled.
LL Diagnostic
Diagnostic for the PLL is available via a diagnostic register. The register contains bits which should never be set
under normal operating conditions. Two bits in the register SEL_XIN or VCO_BYP may be set if the user wishes to
bypass the internal analog PLL or VCO, respectively. The bits are defined in Table 17 - “Diagnostic (DIAG_REG)
Register”.
Bit
7
6
5
4
3
2
1
0
Bit
7:0
PLL_UNLCK
DMAW_OV
MVIP_MST
DMAR_OV
CLK_ERR
FMIC_EN
DMA_EN
RESET
Name
Bits 0 to 7 of the Indirect Address
The bit will be asserted if the on-chip PLL goes out of lock. The ERR pin of the FMIC will
The bit monitors activity on the C4b pin of the MVIP bus and is asserted if there has
When set, enables the FMIC to drive the MVIP clock signals and consequently to
When cleared, all MVIP signals are high impedance and LD0&2 are set to logic 1,
When set, clears all registers in the FMIC control space but does NOT clear connection
also be asserted high. The PLL_UNLCK bit will remain asserted until a zero is written to
it.
When asserted, the bits indicate that a DMA overrun condition occurred on the DMA
Read/Write channel, respectively. The ERR pin of the FMIC will also be asserted. The
DMAR/W_OV bits will remain asserted until zeros are written to them.
been no activity on the C4b pin for 4 ms. The ERR pin of the FMIC will also be asserted
high. The CLK_ERR bit will remain asserted until a zero is written to it
become master of the MVIP bus. When cleared, FMIC becomes slave of MVIP bus.
The bit should be set to enable DMA operations only after the DMA control registers
have been initialized
LD1&3 are set to logic 0. The bit should be set to enable the FMIC to drive data onto the
streams only after the chip has been initialized
and data memory. The bit must be cleared for normal operation
Table 3 - Master Control/Status Register [00]
Table 4 - Low Address Register [01]
Description (This register is cleared upon reset)
Zarlink Semiconductor Inc.
MT90810
14
Bit Function
Data Sheet