mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 16

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

SEL_S8K
EN_SEC8K
0 [000]
1 [001]
2 [010]
3 [011]
4 [100]
Mode
[bits]
Name
X1 divided by
1,2, or 4
SEC8K >DPLL
EX8KA >DPLL
EX8KB >DPLL
MVIP C4
APLL source
Selects source of 8kHz signal driven out on SEC8K pin
0 [00]
1 [01]
2 [10]
3 [11]
Enables SEC8K as output
Table 9 - PLL_MODE Bits (control PLL and frame synchronization)
Mode [bits]
Frame Sync.
no frame
sync.
no frame
sync.
frame sync.
to F0
Figure 6 - Clock Control (CLK_CNTRL) Register
Table 8 - EN_SEC8K and SEL_S8K Bits
SEL_S8K
7
Select EX_8KA as SEC8K output
Select EX_8KB as SEC8K output
Select FRAME as SEC8K output
RESERVED
6
EN_SEC8K
Zarlink Semiconductor Inc.
FMIC as Timing Master
• FMIC defaults to this mode after reset (Clock Control Register
• X1 divided by 1,2 or 4 is used as the input to the APLL.
• State machine is free running and does not synchronize to any
• XCLK_SEL can be programmed to any mode.
• MVIP_MST bit in MCS is set.
• Used when the FMIC is to become the timing master in a
FMIC as MVIP Master (Slaved to external 8 kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
• State machine is not synchronized to external 8 kHz
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS is set.
FMIC as MVIP Slave
• FMIC is entirely slaved to MVIP bus timing.
• MVIP C4 is selected as input to APLL.
• State machine is synchronized to MVIP C4 and F0 inputs.
• MVIP_MST bit in MCS register must be cleared.
5
is cleared).
external 8 kHz source.
system which has no digital network connections (T1 or E1).
is either SEC8K,EX8KA/EX8KB.
(SEC8K/EX8KA/B); that is, FRAME signal is freq locked but not
necessarily phase aligned with external 8 kHz.
MT90810
4
PLL_MODE
16
Description
3
Description
2
XCLK_SEL
1
0
Function
Function
Data Sheet