mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 9

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

In modes 1, 2 and 3, the external clock X1 must be 16.384MHz. This is required for proper operation of the digital
PLL.
The FMIC becomes MVIP master when MVIP_MST bit is set in the Control/Status register.
4. FMIC as MVIP Master (Mode 5,6,7)
In modes 5 through 7, the output of the device’s digital PLL is selected as the input to the analog PLL. The source
to the digital PLL is selected as either SEC8K, EX_8KA or EX_8KB depending on the particular mode (5, 6 or 7)
chosen.
In these modes, the FMIC state machine is synchronized to the external 8kHz input selected, that is, the state
machine output 8 kHz FRAME and F0b signals are phase aligned with the external 8kHz input as well as frequency
locked. Here lies the difference between these modes (5, 6 and 7) and the above mentioned modes (1, 2 and 3). In
these modes, the external 8 kHz input signal is used to synchronize the FMIC state machine.
In modes 5, 6 and 7, the external clock X1 must be 16.384 MHz. This is required for proper operation of the digital
PLL.
The FMIC becomes MVIP master when MVIP_MST bit is set in the Control/Status register.
5. PLL Jitter Performance
To measure the intrinsic jitter of the analog PLL, the FMIC is set to slave mode, slave to a clean MVIP C4 clock (no
jitter). A resulting jitter of 0.004UI p-p is measured on the C2o clock.
The jitter transfer function of the analog PLL, which is the ratio of the output jitter to the input jitter, is shown in
“Figure 5 - Jitter Transfer Function of the Analog PLL”. The measurements are made with a controlled sinusoidal
jitter modulating the MVIP C4 clock.
To measure the intrinsic jitter of the two PLLs combined, the FMIC is set to master mode, slave to a clean external
8 kHz clock SEC8K (no jitter). A resulting jitter of 0.206UI p-p is measured on the C2o clock.
Jitter transfer function of the digital PLL and analog PLL combination is determined primarily by the digital PLL. The
digital PLL is essentially a digital sampler which samples on the nearest rising or falling edge of its 16 MHz clock
and therefore has a 60 ns jitter on the output.
Attenuation
Jitter
(dB)
10
12
14
16
2
4
6
8
1
Figure 5 - Jitter Transfer Function of the Analog PLL
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Zarlink Semiconductor Inc.
Frequency, log scale (Hz)
100
MT90810
9
1K
10K
100K
Data Sheet