mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 35

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mt90810ap

Manufacturer Part Number
mt90810ap
Description
256 X 128 Channels Flexible Mvip Interface Circuit Fmic
Manufacturer
Zarlink Semiconductor
Datasheet
AD[0:7]
(read)
Note:
RDY is only driven low during memory (slow) cycles.
RD
AD[0:7]
(read)
CS
RD
A[0:1]
CS
RDY
WR
AD[0:7]
ALE
Notes:
RDY is only driven low during memory (slow) cycles.
t
RDY
DOFF
is measured from either CS or RD going high, whichever is later.
Figure 20 - Intel Multiplexed Bus Timing for Read Cycle (ALE is active)
Figure 19 - Intel Non-multiplexed Bus Timing (ALE=VSS)
t
t
AS
AS
t
DS
t
AS
t
RDY
Add
t
RDY
t
AH
Zarlink Semiconductor Inc.
MT90810
t
ACC
35
t
ACC
t
DAC
Read Data
t
DAC
t
DOFF
t
t
DH
AH
t
DOFF
Data Sheet

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