mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 23

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

7-4
3
Bit
7:4
Bit
3
2
1
0
RESERVED
CSTo
RESERVED
DC
MC
OE
CAB8
Name
Name
Table 22 - Connection Memory High Bits for Local Channels
Table 21 - Connection Memory High Bits for MVIP Channels
CSTo. The inverted value of this bit is output on the CSTo pin and is available for
general purpose system timing functions. The CSTo bit for each of the local output
channels is multiplexed onto the CSTo pin as illustrated below:
C4
CSTo output timing
F0
LD0:0 LD1:0
Direction Control. controls the direction of the MVIP DSi/DSo channel pair.
When DC is set, DSi is the input channel and DSo is the output channel. When DC
is clear the direction is reversed.
Message Channel. This bit, when set, will send the eight bits of connection memory
low directly out the corresponding output channel and stream. When the bit is
cleared, the contents of the programmed location in connection memory low act as
an address for the data memory and so determine the source of the corresponding
output channels and stream.
Output Enable. This bit, when set, enables the output drivers on a per-channel
basis. This allows individual channels on individual streams to be made high-
impedance, permitting the construction of switch matrices. When this bit is cleared,
the drivers are disable.
Source Channel Address Bit 8. This bit, together with bits CAB0-7 in connection
memory low, is used to select one of 384 different source input channels for the
connection.
Figure 11 - Connection Memory High Byte
RESERVED
7
LD2:0 LD3:0
6
Zarlink Semiconductor Inc.
5
MT90810
4
LD0:1 LD1:1
DC/CSTo
23
3
MC
2
Description
Description
OE/CE
LD2:1 LD3:1
1
CAB8
0
LD0:2 LD1:2
LD2:2 LD3:2
Data Sheet
LD0:3