mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 4

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
35, 36,
37, 38,
42, 43,
44, 45
32, 34
49, 50
47, 48
Pin #
19
29
27
26
25
30
31
10
11
DREQ[0:1
WR/[R/W]
DACK[0:1
[DTACK]
RD/[DS]
RESET
AD[0:7]
Name
A[0:1]
RDY
ERR
TCK
ALE
TDI
CS
]
]
Chip Reset (Schmitt Input). This active low reset clears all internal registers, except
connection memory and data memory.
Microprocessor Address/Data Bus (Bidirectional TTL). Microprocessor access to
internal registers, connection and data memories.
In non-multiplexed mode: data bus.
In multiplexed mode: multiplexed address and data bus.
Microprocessor Address (TTL Input).
In non-multiplexed mode: address to FMIC internal registers
In multiplexed mode: unused (leave unconnected).
Microprocessor Address Latch Enable (TTL Input). Selects the microprocessor
mode.
In Intel multiplexed mode, the falling edge of this signal is used to sample the address.
Microprocessor Bus Chip Select (TTL Input). This active low input enables
microprocessor access to connection and data memory and internal registers.
Read/Data Strobe (TTL Input).
In Intel mode (RD), this active low input configures the data bus lines as output.
In Motorola mode (DS), this active low input operates with CS to enable read and write
operation.
Write\ Read/Write Strobe (TTL Input).
In Intel mode (WR), this active low input configures the data bus lines as inputs.
In Motorola mode (R/W), this input controls the direction of the data bus D[0:7] during a
microprocessor access.
Ready/Data Acknowledge (Open Drain Output).
In Intel mode (RDY), this output acts as IOCHRDY. A 10 K pull up is required.
In Motorola mode (DTACK), this active low output indicates a successful data bus
transfer. A 10 K pull up is required.
Error Status (Output). This pin is asserted high if either a clock error (loss of C4b
clock), DMA overrun condition or PLL unlock occurs.
DMA Request (Output). When DMA operations on the device are enabled, this pin
requests transfers for DMA reads/writes from/to the device.
DMA Acknowledge (TTL Input). When DMA operations on the device are enabled,
this pin receives acknowledgement for DMA reads/writes from/to the device.
JTAG Input Clock (TTL Input). Maximum recommended clock rate is 16 MHz. If not
used, this pin should be left unconnected.
JTAG Serial Input Data (TTL Input). If not used, this pin should be left unconnected.
Zarlink Semiconductor Inc.
MT90810
4
Description
Data Sheet