mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 15

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mt90810ap

Manufacturer Part Number
mt90810ap
Description
256 X 128 Channels Flexible Mvip Interface Circuit Fmic
Manufacturer
Zarlink Semiconductor
Datasheet
Indirect Address
Bits
Bits
7:6
5:4
3:1
7:0
0
13:511
8:11
12
0
1
2
3
4
5
6
7
Auto increment/decrement mode
[00] Normal Mode - indirect address not auto incremented
[01] Auto increment indirect address after indirect read of IDR
[10] Auto increment indirect address after indirect write of IDR
[11] Auto increment indirect address after indirect read or write of IDR
Selects the memory space:
[00] FMIC Control Registers
[01] Data Memory
[10] Connection Memory Low Byte
[11] Connection Memory High Byte
Reserved
Bit 8 of the Indirect Address
All bits are written into the indirect address location specified by the LAR and AMR registers.
If auto increment on write/read is enabled, and connection memory is selected, then consecutive
writes/reads to/from the IDR will toggle between selection of high byte and low byte connection
memory.
CLK_CNTRL
LOC_CLK
SER_MODE
FRMA_STRT
FRMA_MODE
FRMB_STRT
FRMB_MODE
DIAG_REG
RESERVED
Table 7 - FMIC Control Register (read/write)
Name
Table 5 - Address Mode Register [10]
Table 6 - Indirect Data Register [1]
Zarlink Semiconductor Inc.
MT90810
Clock Control Register
Local Output Clock Control
Local Serial Configuration Register
RESERVED
Frame Group A start register
Frame Group A mode register
Frame Group B start register
Frame Group B mode register
RESERVED
Chip diagnostic bits
15
Bit Function
Bit Function
Function
Data Sheet

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