mt90810ap Zarlink Semiconductor, mt90810ap Datasheet - Page 12

• Manufacturer Part Number: mt90810ap
• Description: 256 X 128 Channels Flexible Mvip Interface Circuit Fmic
• Manufacturer: Zarlink Semiconductor

Initialization of the MT90810
The RESET pin should be hold low during initialization and power-up to ensure that all internal registers and
connection and data memories are cleared.
Microprocessor Interface
The FMIC is configured and controlled via a microprocessor interface. The microprocessor interface consists of the
combined address/data bus AD[0:7], address bits A[0:1], the chip select bit CS, the RD and WR signals, the
address latch enable (ALE) signal and the RDY signal. If ALE is tied to VSS, the interface acts as an Intel non
multiplexed interface with the AD[0:7] bus carrying only data and pins A[0:1] serving as the address lines. If ALE is
tied to VCC the interface acts as a Motorola non multiplexed interface using A[0:1] as address lines with RD
becoming DS and WR becoming R/W. If ALE is active (switching during accesses), the interface acts as in Intel
multiplexed interface with the AD[0:7] bus carrying both address and data and the A[0:1] pins unused. The RDY
signal acts as IOCHRDY in Intel mode and as DTACK in Motorola mode.
In all modes the FMIC decodes four read/write registers in the microprocessor’s address space according to Table
2, “FMIC I/O Addresses”.
The microprocessor interface provides read and write access to all the registers. When the microprocessor
performs a read or write to the registers, the microprocessor cycle is a fast cycle (In Intel mode, the RDY bit is not
pulled low, and in Motorola mode, DTACK is asserted immediately). When the microprocessor performs a read or
write to data memory or connection memory, the microprocessor cycle is a slow cycle (In Intel mode, the RDY is
pulled low until the cycle is complete, in Motorola mode DTACK is not asserted until the cycle is complete).
Software Control
The FMIC control registers as well as the connection memory and data memory are accessible through indirect
addressing.
To perform a write operation to an indirect location, the Low Address Register (LAR) and Address Mode Register
(AMR) registers must first be initialized. The lower 8 bits of the indirect address are written to the LAR, and then the
upper bit of the indirect address along with the appropriate bit settings to select the memory and auto
increment/decrement mode is written to the AMR. Finally, the write operation is performed when data is written to
the Indirect Data Register(IDR). Similarly, to perform a read operation from an indirect location, the LAR and AMR
must be initialized and then the data can be read from the IDR.
Data memory can be read and written by the microprocessor. This is accomplished by first initializing the LAR and
AMR register to select data memory and then either reading from or writing to the Indirect Data Register.
Connection memory can be read and written by the microprocessor. This is accomplished by first initializing the
LAR and AMR register to select high or low connection memory and then either reading from or writing to the IDR.
0 [00]
1 [01]
2 [10]
3 [11]
Address
A[1:0]
Table 2 - FMIC I/O Addresses
MCS - Master Control/Status Register
LAR - Low Address Register
AMR - Address Mode Register
IDR - Indirect Data Register
Zarlink Semiconductor Inc.
MT90810
12
Register
Data Sheet