PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 103

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.6.1
Figure 8-1 shows an example of 16-Bit Byte Write
mode for PIC18F85J11 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 8-1:
 2010 Microchip Technology Inc.
Note 1:
PIC18F85J11
2:
16-BIT BYTE WRITE MODE
A<19:16>
AD<15:8>
AD<7:0>
The upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
WRH
WRL
ALE
CE
OE
(1)
16-BIT BYTE WRITE MODE EXAMPLE
373
373
D<7:0>
A<19:0>
D<15:8>
PIC18F85J11 FAMILY
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD<15:0> bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
A<x:0>
D<7:0>
CE
OE
(MSB)
WR
(2)
Address Bus
Data Bus
Control Lines
D<7:0>
DS39774D-page 103
A<x:0>
D<7:0>
CE
OE
(LSB)
WR
(2)