PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 209

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
FIGURE 17-19:
TABLE 17-3:
 2010 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
F
CY
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
SSPM<3:0>
SCL
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
CY
SSPM<3:0>
CY
* 2
Reload
Control
) on the
CLKO
Reload
PIC18F85J11 FAMILY
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD. The SSPADD BRG value of 0x00 is not
supported.
17.4.7.1
When the device is operating in one of the
power-managed modes, the clock source to the BRG
may change frequency, or even stop, depending on the
mode and clock source selected. Switching to a Run or
Idle mode from either the secondary clock or internal
oscillator is likely to change the clock rate to the BRG.
In Sleep mode, the BRG will not be clocked at all.
BRG Down Counter
2
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
0Ch
1Fh
18h
63h
09h
27h
02h
09h
Baud Rate Generation in
Power-Managed Modes
F
OSC
/4
(2 Rollovers of BRG)
400 kHz
400 kHz
333 kHz
312.5 kHz
DS39774D-page 209
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)