PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 91

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 7-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
Unimplemented: Read as ‘0’
FREE: Flash Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by
0 = Perform write only
WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
0 = The write operation completed
WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
0 = Write cycle is complete
Unimplemented: Read as ‘0’
completion of an erase operation)
operation, or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
U-0
—
EECON1: EEPROM CONTROL REGISTER 1
U = Unimplemented bit, read as ‘0’
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
S = Settable bit (cannot be cleared in software)
‘0’ = Bit is cleared
PIC18F85J11 FAMILY
WRERR
R/W-x
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS39774D-page 91
U-0
—
bit 0