PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 141

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 11-11: PORTE FUNCTIONS
 2010 Microchip Technology Inc.
RE0/RD/AD8
RE1/WR/AD9
RE2/AD10/CS
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15/
CCP2
Legend:
Note 1:
Pin Name
2:
3:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don’t care (TRIS bit
does not affect port direction or is overridden for this option).
Available on 80-pin devices only.
External memory interface I/O takes priority over all other digital and PSP I/O.
Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Function
CCP2
AD10
AD11
AD12
AD13
AD14
AD15
AD8
AD9
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
WR
RD
CS
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
Setting
TRIS
0
1
1
x
x
0
1
1
x
x
0
1
x
x
1
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATE<0> data output.
PORTE<0> data input.
Parallel Slave Port read enable control input.
External memory interface, address/data bit 8 output.
External memory interface, data bit 8 input.
LATE<1> data output.
PORTE<1> data input.
Parallel Slave Port write enable control input.
External memory interface, address/data bit 9 output.
External memory interface, data bit 9 input.
LATE<2> data output.
PORTE<2> data input.
External memory interface, address/data bit 10 output.
External memory interface, data bit 10 input.
Parallel Slave Port chip select control input.
LATE<3> data output.
PORTE<3> data input.
External memory interface, address/data bit 11 output.
External memory interface, data bit 11 input.
LATE<4> data output.
PORTE<4> data input.
External memory interface, address/data bit 12 output.
External memory interface, data bit 12 input.
LATE<5> data output.
PORTE<5> data input.
External memory interface, address/data bit 13 output.
External memory interface, data bit 13 input.
LATE<6> data output.
PORTE<6> data input.
External memory interface, address/data bit 14 output.
External memory interface, data bit 14 input.
LATE<7> data output.
PORTE<7> data input.
External memory interface, address/data bit 15 output.
External memory interface, data bit 15 input.
CCP2 compare output and CCP2 PWM output; takes priority over
port data.
CCP2 capture input.
PIC18F85J11 FAMILY
Description
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DS39774D-page 141
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