PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 194

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F85J11 FAMILY
17.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-Bit Addressing mode and up to
63 addresses in 10-Bit Addressing mode (see
Example 17-2).
The I
address masking is used or not. However, when
address masking is used, the I
Acknowledge multiple addresses and cause interrupts.
When this occurs, it is necessary to determine which
address caused the interrupt by checking SSPBUF.
In 7-Bit Addressing mode, Address Mask bits,
ADMSK<5:1> (SSPCON2<5:1>), mask the correspond-
ing address bits in the SSPADD register. For any ADMSK
bits that are set (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). For the module
EXAMPLE 17-2:
DS39774D-page 194
7-Bit Addressing:
10-Bit Addressing:
2
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1>
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK<5:1>
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
C Slave behaves the same way, whether
Address Masking
ADDRESS MASKING EXAMPLES
= 00111
= 00111
2
C slave can
to issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
In 10-Bit Addressing mode, ADMSK<5:2> bits mask
the corresponding address bits in the SSPADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD<1:0>). For any ADMSK
bits that are active (ADMSK<n> = 1), the correspond-
ing address bit is ignored (SSPADD<n> = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
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