MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 125

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
SPSCK — SPI Serial Clock
MOSI — Master Out/Slave In
MISO — Master In/Slave Out
SS — Slave Select
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the
output buffer.
DDRD7–DDRD0 — Data Direction Register D Bits
Freescale Semiconductor
The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level
select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer
channel I/O pins or general-purpose I/O pins. See
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the
PTD3/SPSCK pin is available for general-purpose I/O.
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTD2/MOSI pin is available for general-purpose I/O.
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTD1/MISO pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRD0 bit in data direction register D (DDRD) has no effect on the PTD0/SS pin.
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port
D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
DDRD7
$0007
Bit 7
0
Figure 12-14. Data Direction Register D (DDRD)
DDRD6
6
0
MC68HC908GP32 Data Sheet, Rev. 10
DDRD5
5
0
NOTE
DDRD4
4
0
Table
Chapter 17 Timer Interface Module
DDRD3
12-5.
3
0
DDRD2
2
0
DDRD1
1
0
DDRD0
Bit 0
0
(TIM).
Port D
125