MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 212

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timer Interface Module (TIM)
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
ELSxB and ELSxA — Edge/Level Select Bits
When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is
available as a general-purpose I/O pin.
ELSxB and ELSxA bits.
212
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See
17-3. Reset clears the MSxA bit.
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Table
MSxB:MSx
X0
X1
1X
1X
1X
00
00
00
01
01
01
01
A
17-3.
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB:ELSx
00
00
01
10
11
00
01
10
11
01
10
11
A
Table 17-3. Mode, Edge, and Level Selection
MC68HC908GP32 Data Sheet, Rev. 10
Output compare or PWM
Table 17-3
Buffered output
buffered PWM
Output preset
Input capture
compare or
Mode
NOTE
shows how ELSxB and ELSxA work. Reset clears the
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising or falling edge
Capture on falling edge only
Capture on rising edge only
Toggle output on compare
Toggle output on compare
Clear output on compare
Clear output on compare
Software compare only
Set output on compare
Set output on compare
Configuration
Freescale Semiconductor
Table