MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 73

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PRE1 and PRE0 — Prescaler Program Bits
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
5.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
Freescale Semiconductor
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
5.3.3 PLL Circuits
PLLON bit is set. Reset clears these bits.
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See
Register.) controls the hardware center-of-range frequency, f
the PLLON bit is set. Reset clears these bits.
•
•
•
•
Selects automatic or manual (software-controlled) bandwidth control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking mode
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
5.3.8 Base Clock Selector
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
5.3.3 PLL
1. Do not program E to a value of 3.
and
PRE1 and PRE0
VPR1 and VPR0
Circuits,
5.3.6 Programming the
00
01
10
11
00
01
10
11
Table 5-2. PRE1 and PRE0 Programming
Table 5-3. VPR1 and VPR0 Programming
5.3.6 Programming the
MC68HC908GP32 Data Sheet, Rev. 10
Circuit.)
NOTE
PLL.) PRE1 and PRE0 cannot be written when the
3
P
E
0
1
2
3
0
1
2
(1)
PLL, and
VRS
Prescaler Multiplier
VCO Power-of-Two
. VPR1:VPR0 cannot be written when
Range Multiplier
5.5.5 PLL VCO Range Select
1
2
4
8
1
2
4
8
CGM Registers
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