MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 158

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
158
Addr.
$FE00
$FE01
$FE02
PIN LOGIC
RESET
Note: Writing a logic 0 clears SBSW.
SIM Break Status Register
SIM Reset Status Register
SIM Upper Byte Address
Register Name
Register (SUBAR)
V
DD
INTERNAL
PULLUP
DEVICE
(SRSR)
(SBSR)
SIM RESET STATUS REGISTER
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
POR:
RESET PIN CONTROL
Figure 14-2. SIM I/O Register Summary
POR CONTROL
AND PRIORITY DECODE
STOP/WAIT
INTERRUPT CONTROL
CONTROL
CONTROL
CLOCK
Figure 14-1. SIM Block Diagram
Bit 7
POR
MC68HC908GP32 Data Sheet, Rev. 10
R
R
1
= Unimplemented
PIN
6
R
R
0
CLOCK GENERATORS
RESET
COUNTER
SIM
COP
÷ 2
5
R
R
0
CONTROL
MASTER
RESET
ILOP
4
R
R
R
0
= Reserved
ILAD
R
R
3
0
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
MODRST
R
R
2
0
Freescale Semiconductor
SBSW
Note
LVI
1
R
0
0
Bit 0
R
R
0
0