MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 193

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

SPR1 and SPR0 — SPI Baud Rate Select Bits
Use this formula to calculate the SPI baud rate:
15.13.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data
register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data
register reads data from the receive data register. The transmit data and receive data registers are
separate registers that can contain different values. (See
R7–R0/T7–T0 — Receive/Transmit Data Bits
Freescale Semiconductor
In master mode, these read/write bits select one of four baud rates as shown in
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Address: $0012
Do not use read-modify-write instructions on the SPI data register since the
register read is not the same as the register written.
Reset:
Read:
Write:
SPR1 and SPR0
Bit 7
R7
T7
00
01
10
11
Baud rate
Table 15-4. SPI Master Baud Rate Selection
Figure 15-15. SPI Data Register (SPDR)
R6
T6
6
MC68HC908GP32 Data Sheet, Rev. 10
=
BUSCLK
----------------------- -
2 BD
R5
T5
5
×
NOTE
Unaffected by reset
R4
T4
4
Baud Rate Divisor (BD)
Figure
R3
T3
3
128
32
15-2.)
2
8
R2
T2
2
R1
T1
1
Table
Bit 0
R0
T0
15-4. SPR1 and
I/O Registers
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